During the fabrication of a semiconductor design, process variations during fabrication may affect the performance of a metal oxide semiconductor field effect (MOSFET) transistor. Process variations may be primarily due to physical factors such as variations in gate oxide thickness, doping concentrations, and transistor channel length, among other factors. These physical factors may be characterized by parameters in process models that capture circuit performance changes based on parameter variations. The process models are called process corners, because the circuit performances resulting from the process model variations may be characterized as typical, slow, or fast.
Threshold voltage and/or electron mobility are process corner parameters that are critical to transistor performance. The threshold voltage of a transistor represents the voltage point where the gate to source voltage of a transistor turns on the transistor to an active conducting state. Slight changes in threshold voltage often produce significant changes in transistor performance. The performance of an n-channel MOSFET (nMOS) transistor and a p-channel MOSFET (pMOS) transistor may be individually characterized as fast, slow, or typical performance relative to the threshold voltage of a particular process corner.
For example, in a particular process corner, the performance of the nMOS transistors may be slow and the performance of the pMOS transistors may be slow. Therefore, the process corner is characterized as a slow-slow (SS) corner, i.e., slow nMOS and slow pMOS. Similarly, there may be the fast-fast (FF) process corner, i.e., fast nMOS, fast pMOS; fast-slow (FS) process corner, i.e., fast nMOS and slow pMOS; and slow-fast process corner (SF), slow nMOS and fast pMOS.
The implementation of some types of integrated circuits, such as pre-emphasis and de-emphasis devices and clock circuitry, may require a certain amount of delay. The delay is typically implemented using a simple CMOS-based inverter chain.
FIG. 1 illustrates a typical inverter chain delay line 100 having a number of stages. It must be noted that the number of inverter stages may vary depending on implementation. An input 10 to delay line 100 may produce a delayed output 80. The delay through inverter chain 100 is not constant and may vary, e.g., up to a 4× change in delay, across different process corners. For example, the delay through an inverter in an FF process corner may be 20 picoseconds (ps). The delay through the same inverter in a SS process corner may increase to 80 ps. The delay increase represents a 4× change in delay from the FF process corner to the SS process corner. This delay variation impacts circuit performance, for example, the maximum speed at which the circuit can operate.